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note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, llc reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no respon - sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: generation 4 and 5 devices for existing customer transition, and for new customers or new appli - cations, contact allegro sales. single lnb supply and control voltage regulator a8303 and A8303-1 date of status change: december 5, 2018 this device is in production, however, it has been deemed pre-end of life. the product is approaching end of life. within a minimum of 6 months, the device will enter its final, last time buy, order phase. pre-end-of-life
description intended for analog and digital satellite receivers, these single low noise block converter regulator (lnbr) are monolithic linear and switching voltage regulators, specifically designed to provide the power and the interface signals to an lnb down converter via coaxial cable. the a8303 and A8303-1 require few external components, with the boost switch and compensation circuitry integrated inside of the devices. a high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. the high levels of component integration ensure extremely low noise and ripple figures. the a8303 and A8303-1 have been designed for high efficiency, using the allegro ? advanced bcd process. the integrated boost switch has been optimized to minimize both switching and static losses. to further enhance efficiency, the voltage drop across the tracking regulator has been minimized. for diseqc? communications, a tone control pin is provided to gate the internally generated 22 khz tone on-and-off. a comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good. furthermore, design methodology and structure ensure the highest level of robustness against transients and component failures. the devices use a 2-wire bidirectional serial interface, compatible with the i 2 c? standard, that operates up to 400 khz. the a8303 and A8303-1 are supplied in a lead (pb) free package. 8303-ds, rev. 9 mco-0000367 features and benefits ? integrated boost mosfet, current sensing, and compensation ? stable with low-profile ceramic boost capacitors ? configurable output settings to meet global requirements ? A8303-1 includes 11.667 v setting to meet japanese market requirements ? adjustable lnb output current limit from 250 to 950 ma covers wide array of application requirements minimizes component sizing to fit each application for startup, reconfiguration, and continuous output (maximum value depends on pcb thermal design) ? boost peak current limit scales with lnb current limit setting ? 8 programmable lnb output voltage (dac) levels ? lnb overcurrent limiter with shutdown timer ? static lnb current limit reliably starts a wide range of loads ? tracking boost converter minimizes power dissipation ? lnb transition times configurable by external capacitor single lnb supply and control voltage regulator functional block diagram a8303 and A8303-1 package: 20-contact mlp/qfn (suffix es) 4 mm 4 mm 0.75 mm continued on the next page february 8, 2019 i 2 c interface linear regulat o r boost regulator slew rate l imiter + i c power 3 52 khz osc 0. 8 v la tched faults uvlo , ocp, t s d unlatched s tatus png, cpo k t s d dac read r s t s e t lnb r ef b o ost r ef o c boost l x gndlx v i n gnd tcap tonectrl sda scl add t i m e r 45 m s vre g r ef vsel 2 / 1 / 0 v in clk 3 t o n e d ete c tor tdo irq f ault vcp charge p u m p o n / off 22 khz t o n e generato r + lnb i s e t tdi a d j tde t i li m v f b v in
2 selection guide part number output voltage settings packing [1] description a8303sestr-t refer to table 3a 7 in. reel, 1500 pieces/reel 12 mm carrier tape es package [2] , mlp/qfn surface mount 4 mm 4 mm 0.75 mm nominal height a8303sestr-t-1 refer to table 3b [1] contact allegro for additional packing options. [2] leadframe plating 100% matte tin. absolute maximum ratings characteristic symbol conditions rating unit load supply voltage, vin pin v in 30 v output current [3] i out internally limited a output voltage: boost pin C0.3 to 43 v output voltage: lnb pin surge [4] C1.0 to 43 v output voltage: lx pin C0.3 to 30 v output voltage: vcp pin C0.3 to 48 v logic input voltage C0.3 to 5.5 v logic output voltage C0.3 to 5.5 v operating ambient temperature t a range s C20 to 85 c junction temperature t j (max) 150 c storage temperature t stg C55 to 150 c [3] output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current ratings, or a junction temperature, t j , of 150c. [4] see application schematics 3 and 4 on pages 24 and 25. ? push-pull lnb output stage maintains 13 18 v and 18 13 v transition times, even with highly capacitive loads ? built-in 22 khz tone oscillator facilitates diseqc? tone encoding, even at no-load ? tone generation does not require additional external components ? diagnostic features: png, tdet ? dynamic tone detect amplitude and frequency transmit/ receive thresholds ? extensive protection features: uvlo, ocp, tsd, cpok ? 2-wire i 2 c-compatible interface features and benefits ( continued ) thermal characteristics characteristic symbol test conditions [5] value unit package thermal resistance r - 4-layer pcb based on jedec standard 37 c/w [5] additional thermal information available on the allegro website. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
3 table of contents features and benefits ........................................................... 1 description .......................................................................... 1 package ............................................................................. 1 functional block diagram ..................................................... 1 selection guide ................................................................... 2 absolute maximum ratings ................................................... 2 thermal characteristics ........................................................ 2 pinout diagram and terminal list ........................................... 4 electrical characteristics ....................................................... 5 functional description .......................................................... 8 protection ........................................................................ 8 boost converter/linear regulator ....................................... 8 charge pump ............................................................... 8 lnb and boost current limit setting ................................ 8 slew rate control ......................................................... 9 pull-down rate control .................................................. 9 pull-down rate control .................................................. 9 odt (overcurrent disable time) ......................................... 9 short circuit handling ........................................................ 9 auto-restart ..................................................................... 9 in-rush current .............................................................. 10 tone generation ............................................................. 10 tone detection ............................................................... 10 component selection ....................................................... 11 boost inductor .............................................................. 11 boost capacitors ......................................................... 12 boost capacitors ......................................................... 14 surge components ...................................................... 14 boost filtering and lnb noise ................................... 14 surge components ...................................................... 14 i 2 c?-compatible interface .............................................. 15 sda and scl signals .................................................. 15 acknowledge (ak) bit .................................................. 15 acknowledge bit during a write sequence ..................... 15 acknowledge bit during a read sequence ..................... 15 i 2 c? communications ................................................... 16 i 2 c? start and stop conditions ................................... 16 i 2 c? write cycle description ....................................... 16 i 2 c? read cycle description ....................................... 16 interrupt (irq) and fault clearing ..................................... 17 control registers (i 2 c?-compatible write register) ........... 21 status register (i 2 c?-compatible read register) .............. 22 application information ....................................................... 23 package outline drawing .................................................... 28 single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
4 pinout diagram terminal list table name number function add 9 address select boost 20 tracking supply voltage to linear regulator gnd 14 signal ground gndlx 17 boost switch ground irq 6 interrupt request iset 12 output current limit set via external resistor lnb 2 output voltage to satellite dish lx 16 inductor drive point nc 3,18,19 no connection pad pad exposed pad; connect to the ground plane, for thermal dissipation scl 7 i 2 c?-compatible clock input sda 8 i 2 c?-compatible data input/output tcap 11 capacitor for setting the rise and fall time of the lnb output tdi 4 connect to output for 22 khz tone verification function tdo 5 open-drain logic output that transitions low when a 22 khz tone is present at tdi tonectrl 10 gates the 22 khz tone on-and-off vcp 1 gate supply voltage vin 15 supply input voltage vreg 13 analog supply single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com pa d 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 boost nc nc gndlx lx irq scl sda add to nectrl vin gnd vreg iset tcap vcp lnb nc tdi tdo
5 electrical characteristics [1] : valid at t a = 25c, v in = 10 to 16 v, as noted [2] , unless noted otherwise characteristics symbol test conditions min. typ. max. unit general output voltage accuracy v out v in = 12 v, i out = 50 ma, see tables 3a and 3b for dac settings C2 C 2 % load regulation v out(load) v in = 12 v, v out = 13.667 v, i out = 50 to 700 ma C 75 120 mv v in = 12 v, v out = 19.000 v, i out = 50 to 700 ma C 85 150 mv line regulation v out(line) v in = 10 to 16 v, v out = 13.667 v, i out = 50 ma C10 0 10 mv v in = 10 to 16 v, v out = 19.000 v, i out = 50 ma C10 0 10 mv supply current i in(off) enb = 0, v in = 12 v C 4 C ma i in(on) enb = 1, v in = 12 v, v out = 19 v, i load = 0 ma, tonectrl = 0 C 11 C ma enb = 1, v in = 12 v, v out = 19 v, i load = 0 ma, tonectrl = 1 C 17 C ma boost switch on resistance r ds(on) boost i sw = 450 ma C 300 C m? switching frequency f sw 320 352 384 khz linear regulator voltage drop ?v reg v boost C v lnb , no tone signal, i load = 700 ma 600 800 1000 mv tcap pin current i tcap tcap capacitor (c12) charging C13 C10 C7 a tcap capacitor (c12) discharging 7 10 13 a output voltage rise time [3] t r(vlnb) for v lnb 13.667 to 19.667 v; c 12 = 100 nf, i load = 700 ma C 10 C ms output voltage pull-down time [3] t f(vlnb) for v lnb 19.667 to 13.667 v; c load = 100 f, i load = 0 ma C 25 C ms lnb sink current [3] i rlnb enb = 0, v lnb = 21 v, boost capacitor fully charged C 2 4 ma enb = 1, vsel 2,1,0 = 001 (13.667 v), v lnb = 21 v, tonectrl = 0 or 1 C 9 15 ma enb = 1, vsel 2,1,0 = 101 (19.000 v), v lnb = 21 v, tonectrl = 0 or 1 C 9 15 ma enb = 1, vsel 2,1,0 = 110 (19.667 v), 18.5 v < v lnb <21 v, tonectrl = 0 C 30 40 ma lnb off current i lnb(off) v in = 16 v C C 10 a continued on the next page single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
6 electrical characteristics [1] (continued): valid at t a = 25c, v in = 10 to 16 v, as noted [2] , unless noted otherwise characteristics symbol test conditions min. typ. max. unit general (continued) ripple and noise on lnb output [4] v rip,n(pp) 20 mhz bwl; reference circuit shown in application information section; contact allegro for additional information on application circuit board design C 15 C mv pp vreg voltage v vreg v in = 10 v 4.97 5.25 5.53 v iset voltage v iset v in = 10 v 3.4 3.5 3.6 v tcap voltage v tcap v in = 10 v, v out = 13.667 v C 2.28 C v v in = 10 v, v out = 19.000 v C 3.17 C v protection circuitry output overcurrent limit [5] i out(max) r set = 100 k? 250 300 350 ma r set = 37.4 k? 720 800 880 ma overcurrent disable time t dis C 45 C ms vin undervoltage lockout threshold v uvlo v in falling 8.05 8.35 8.65 v vin turn on threshold v in(th) v in rising 8.40 8.70 9.00 v undervoltage hysteresis v uvlohys C 350 C mv boost mosfet current limit i boost(max) r set = 100 k? C 1680 C ma r set = 37.4 k? C 4030 C ma thermal shutdown threshold [3] t j C 165 C c thermal shutdown hysteresis [3] ?t j C 20 C c power not good (low) png loset with respect to v lnb setting; v lnb low, png set to 1 88 91 94 % png loreset with respect to v lnb setting; v lnb low, png reset to 0 92 95 98 % power not good (low) hysteresis png lohys with respect to v lnb setting C 4 C % power not good (high) png hiset with respect to v lnb setting; v lnb high, png set to 1 106 109 112 % png hireset with respect to v lnb setting; v lnb high, png reset to 0 102 105 108 % power not good (high) hysteresis png hihys with respect to v lnb setting C 4 C % tone amplitude (a8303) v tone(pp) i lnb = 0 to 700 ma, c lnb = 750 nf 400 650 900 mv pp amplitude (A8303-1) v tone(pp) i lnb = 0 to 700 ma, c lnb = 330 nf 400 650 800 mv pp frequency f tone i lnb = 0 to 700 ma, c lnb = 750 nf or 330 nf 20 22 24 khz duty cycle dc tone 40 50 60 % rise time t r(tone) 5 10 15 s fall time t f(tone) 5 10 15 s continued on the next page single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
7 tone detection amplitude v tdx(pp) tonectrl = 1 400 650 900 mv pp v tdr(pp) tonectrl = 0; 22 khz sine wave 250 650 900 mv pp reject amplitude, low v td(xmt)l tonectrl = 1 C C 250 mv pp v td(rcv)l tonectrl = 0; 22 khz sine wave C C 100 mv pp reject amplitude, high v td(xmt)h tonectrl = 1 C C 1100 mv pp v td(rcv)h tonectrl = 0; 22 khz sine wave C C 1100 mv pp frequency capture f td(rcv) tonectrl = 0; 650 mv pp sine wave 17 22 27 khz f td(xmt) tonectrl = 1; 650 mv pp sine wave 20 22 24 khz frequency reject, low f td(rcv)l tonectrl = 0; 650 mv pp sine wave 12 14 C khz f td(xmt)l tonectrl = 1; 650 mv pp sine wave 15 17 C khz frequency reject, high f td(rcv)h tonectrl = 0; 650 mv pp sine wave C 34 37 khz f td(xmt)h tonectrl = 1; 650 mv pp sine wave C 30 33 khz detection delay t det 650 mv pp , 22 khz sine wave C 1.5 3 cycle tdi input impedance z tdi C 8.6 C k tdo output voltage v tdo(l) tone present, i load = 3 ma ? ? 0.4 v tdo output leakage i tdo tone absent, 0 v < v tdo < 5 v ? ? 10 a tone control (tonectrl) logic input v h 2.0 C C v v l C C 0.8 v input leakage C1 C 1 a i 2 c?-compatible interface logic input (sda,scl) low level v scl(l) C C 0.8 v logic input (sda,scl) high level v scl(h) 2.0 C C v logic input hysteresis v i2cihys C 150 C mv logic input current i i2ci v i2ci = 0 to 5 v C1 <1.0 1 a logic output voltage sda and irq v out(l) i load = 3 ma C C 0.4 v logic output leakage sda and irq v lkg v out = 0 to 5 v C C 10 a scl clock frequency f clk C C 400 khz i 2 c? address setting add voltage for address 0001,000 address1 0 C 0.7 v add voltage for address 0001,001 address2 1.3 C 1.7 v add voltage for address 0001,010 address3 2.3 C 2.7 v add voltage for address 0001,011 address4 3.3 C 5.0 v [1] operation at 16 v may be limited by power loss in the linear regulator. [2] indicates specifications guaranteed from 0 t j 125c min . [3] guaranteed by worst case process simulations and system characterization. not production tested. [4] lnb output ripple and noise are dependent on component selection and pcb layout. refer to the application schematic and pcb layout recommendations. not production tested. [5] current from the lnb output may be limited by the choice of boost components. electrical characteristics [1] (continued): valid at t a = 25c, v in = 10 to 16 v, as noted [2] , unless noted otherwise characteristics symbol test conditions min. typ. max. unit single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
8 protection the a8303 and A8303-1 have a wide range of protection features and fault diagnostics which are detailed in the status register section. boost converter/linear regulator the a8303 and A8303-1 solution contains a tracking current- mode boost converter and linear regulator. the boost converter tracks the requested lnb voltage to within 800 mv, to minimize power dissipation. under conditions where the input voltage, v boost , is greater than the output voltage, v lnb , the linear regu - lator must drop the differential voltage. when operating in these conditions, care must be taken to ensure that the safe operating temperature range of the a8303 and A8303-1 is not exceeded. the boost converter operates at 352 khz typical: 16 times the internal 22 khz tone frequency. all the loop compensation, current sensing, and slope compensation functions are provided internally. the a8303 and A8303-1 have internal pulse-by-pulse current limiting on the boost converter and dc current limiting on the lnb output to protect the ic against short circuits. when the lnb output is shorted, the lnb output current is limited, and if the overcurrent condition lasts for more than 45 ms, the lnb output will be disabled. if this occurs, the a8303 and A8303-1 output must be reenabled for normal operation. the system should provide sufficient time between successive restarts to limit internal power dissipation; 1 to 2 seconds is recommended at extremely light load or no load, if the boost voltage tries to exceed the boost target voltage, the boost converter oper - ates with minimum on time. boost settling voltage depends on supply voltage, boost inductance, minimum on time, switching frequency, output power and power loss in boost inductor, capaci - tor and a8303 and A8303-1. if the boost voltage settles below pulse skipping threshold (23.7 v), the boost converter continues to operate with minimum on time. if boost voltage tries to exceed 23.7 v, pulse skipping occurs, and pulse skipping stops when the boost voltage drops to 23.4 v. in the case that two or more set top box lnb outputs are con - nected together by the customer (e.g., with a splitter), it is pos - sible that one output could be programmed at a higher voltage than the other. this would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 v on the output of a 13 v programmed voltage). the output with the highest voltage will effectively turn off the other outputs. as soon as this voltage is reduced below the value of the other outputs, the a8303 and A8303-1 output will auto-recover to their programmed levels. charge pump. generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. lnb and boost current limits. the lnb output current limit, i out(max) can be set by connecting a resistor (rset) from the iset pin to gnd as shown in the applications schematic. the lnb current limit can be set from 300 to 800 ma, correspond - ing to an r set value of 100 to 37.4 k, respectively. if the lnb current limit is exceeded for more than the overcurrent disable time (t dis ) then the a8303 and A8303-1 will be shut down and the ocp bit set, as shown in figure 1. the lnb output current limit can be set as high as 950 ma (r set = 31.6 k) but care should be taken not to exceed the thermal limit of the package or thermal shutdown (tsd) will occur. the typical lnb output cur - rent limit can be set according to the following equation: i out(max) = 29,925 / r set , where i out(max) is in ma and r set is in k. if the voltage at the iset pin is 0 v (that is, shorted to gnd), i out(max) will be clamped to a moderately high value (approximately 1.5 a). care should be taken to ensure that iset is not inadvertently grounded. if no resistor is connected to the iset pin (that is, if iset is open-circuit), i out(max) will be set to approximately 0 a and the a8303 and A8303-1 will not support any load (ocp will occur prematurely). the boost pulse-by-pulse current limit, i boost(max) , is auto - matically scaled along with the lnb output current limit. the typical boost current limit is set according to the following equation: i boost(max) = 4.7 i out(max) + 270 ma , where both i boost(max) and i out(max) are in ma. automatically scaling the boost current limit allows the designer to choose the lowest possible saturation current of the boost inductor, reducing its physical size and pcb area, thus minimizing cost. functional description single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
9 figure 1. startup, reconfiguration, and short circuit operation using r set = 37.4 k, and a capacitive load slew rate control. during either start-up, or when the output voltage at the lnb pin is transitioning, the output voltage rise and fall times can be set by the value of the capacitor connected from the tcap pin to gnd (c12 in the applications schematic). note that during start-up, the boost pin is pre-charged to the input voltage minus a diode voltage drop. as a result, the slew rate control for the boost pin occurs from this voltage. the value of c12 can be calculated using the following formula: c 12 = ( i tcap 6) / sr , where sr is the required slew rate of the lnb output voltage, in v/s, and i tcap is the tcap pin current specified in the electrical characteristics table. the recommended value for c 12 , 100 nf, should provide satisfactory operation for most applications. the minimum value of c 12 is 10 nf. there is no theoretical maxi - mum value of c 12 however too large a value will probably cause the voltage transition specification to be exceeded. tone genera - tion is unaffected by the value of c 12 . pull-down rate control. in applications that have to oper - ate at very light loads and that require large load capacitances (in the order of tens to hundreds of microfarads), the output linear stage provides approximately 45 ma of pull-down capability. this ensures that the lnb output voltage is ramped from 18 to 13 v in a reasonable amount of time. when the tone is on (tonectrl = 1), the output linear stage must increase its pull-down capability to approximately 100 ma. this ensures that the tone signal meets all specifications, even with no load on the on the lnb output. odt (overcurrent disable time) if the lnb output current exceeds the set output current, for more than 45 ms, then the lnb output will be disabled and the ocp bit will be set. see figure 1. short circuit handling if the lnb output is shorted to ground, the lnb output current will be clamped to i out(max) . if the short circuit condition lasts for more than 45 ms, the a8303 and A8303-1 will be disabled and the ocp bit will be set. auto-restart after a short circuit condition occurs, the host controller should periodically reenable the a8303 and A8303-1 to check if the short circuit has been removed. consecutive startup attempts should allow 1 to 2 seconds of delay between restarts. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
10 in-rush current at start-up or during an lnb reconfiguration event, a transient surge current above the normal dc operating level can be pro - vided by the a8303 and A8303-1 . this current increase can be as high as the set output current, for as long as required, up to a maximum of 45 ms. tone generation a 22 khz tone is generated internally, and can be controlled on and off via the tonectrl pin as shown in figure 2. note this tone can be generated under no-load conditions, and does not require the use of an external diseqc filter. tone detection a 22 khz tone detector is provided in the a8303 and A8303-1. the detector extracts the 22 khz signal from the ac-coupled tdi pin and provides it as an open-drain logic output at the tdo pin. also, when a tone is present, the tdet bit in the status register is set high and can be seen via the i 2 c interface. the tone detec - tion delay is typically shorter than 1.5 cycles. the tone detector dynamically adjusts its amplitude and fre - quency thresholds depending on whether the a8303 and A8303-1 are transmitting or receiving a tone signal. if tonectrl is a logic high, the a8303 and A8303-1 are transmitting and the tone detect amplitude threshold is relatively high and the acceptable frequency range is tight. this guarantees a high quality tone signal is always generated by the a8303 and A8303-1. on the other hand, if tonectrl is a logic low, the a8303 and A8303-1 are receiving and the tone detect amplitude threshold is reduced and the acceptable frequency range is increased slightly. this guarantees the a8303 and A8303-1 have maximum sensitivity to remotely generated tone signals that may be degraded by long lengths of coaxial cable. the electrical characteristics table of this datasheet documents the guaranteed specifications of the tone detector and how they are adjusted by tonectrl. to help in the understanding, typical tone detector operation is shown graphically in figures 3a and 3b. the shaded areas in figure 3a indicate the accept range of the detector when tonectrl is a logic high (transmit) and a logic low (receive). the shaded areas in figure 3b indicate the reject range of the detector when tonectrl is a logic high (transmit) and a logic low (receive). figure 2. internal tone, gated by tonectrl pin tonectrl = 1 (transmit) tonectrl = 0 (receive) tone frequency (khz) 900 400 250 17 20 24 27 tone amplitude (mv) tonectrl = 1 (transmit) tonectrl = 0 (receive) tone frequency (khz) 1100 250 100 12 15 37 33 tone amplitude (mv) figure 3a. accept ranges of tone detection feature figure 3b. reject ranges of tone detection feature single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com tonectrl tone (lnb ref) lnb (v)
11 component selection boost inductor the a8303 and A8303-1 are designed to operate with a boost inductor value of 15 h +30%/C40% with a dcr less than 75 m?. the error amplifier loop compensation, current sense gain, and pwm slope compensation were chosen for this value of inductor. the boost inductor must be able to support the peak currents required to maintain the maximum lnb output current without saturating. figure 4 can be used to determine the peak current in the inductor given the lnb load current. the typical curve uses v in = 12 v, v out = 19 v, l = 15 h, and f = 352 khz, while the maximum curve assumes v in = 9 v, v out = 20 v, l = 12 h, and f = 282 khz. the system will have reduced gain and phase margins, if the boost inductor is higher than 22 h. figure 6 shows a bode plot of the boost loop with 3 10 f of boost capacitance and 33, 22, 18, 15, and 10 h of boost inductance. although this plot assumes many of the system variables are worst case (10.8 v in , 20 v out , +2% dac tolerance, 1v of v reg , 1.1 a load, and 320 khz), these conditions could certainly occur in an appli - cation. this plot shows that, as the boost inductance increases, the 0 db crossover frequency remains relatively constant but the phase and gain margins are reduced. with 22 h, the phase mar - gin is 32 and with 33 h the phase margin is only 10. figure 6. gain and phase margin of the boost loop at various inductance levels figure 4. boost inductor peak current versus i lnb 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 100 200 300 400 maximum i lnb (ma) i boost (ma peak) typical 500 600 700 800 900 single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
12 figure 5. boost capacitor rms current versus i lnb 1100 1000 900 800 700 600 500 400 300 200 100 200 300 400 maximum i lnb (ma) i boost (ma rms) typical 500 600 700 800 900 boost capacitors the a8303 and A8303-1 are designed to operate with two or three, high-quality ceramic capacitors on the boost node. allegro recommends capacitors that are rated at least 35 v, 10%, x7r, 1210 size. physically smaller capacitors, like 0603 and 0805, with lower temperature ratings, like x5r and z5u, should be avoided. figure 5 can be used to determine the necessary rms current rating of the boost capacitor given the lnb load current. the typical curve uses v in = 12 v, v out = 19 v, l = 15 h, and f = 352 khz while the maximum curve assumes v in = 9 v, v out = 20 v, l = 12 h, and f = 282 khz. the nominal boost capacitance should total 18.8 to 30 f. allegro recommends either four 4.7 f or three 10 f capacitors, with the characteristics shown in table 1. if tolerance, tempera - ture, and dc bias effects are considered, the capacitance must total at least 13 f. the dc bias effect is very significant on ceramic capacitors with lower voltage ratings, smaller packages, or wider temperature characteristics. for example, a 10 f, 25 v, 1206, x5r capacitor can lose 85% of its value at 20 vdc bias. if the total boost capacitance becomes less than 12 f, the converter will have reduced gain and phase margins. if the total boost capacitance becomes less than 7.5 f, then the converter will very likely be unstable. figure 7 shows a bode plot of the boost loop with 15 h of boost inductance and 20, 15, 10, 7.5, and 5 f of boost capacitance. although this plot assumes many of the system variables are worst case (10.8 v in , 20 v out , +2% dac tolerance, 1 v of v reg , 1.1 a load, and 320 khz), these conditions could cer - tainly occur in an application. this plot shows that, as the boost capacitance decreases, the 0 db crossover frequency increases and the phase and gain margins are reduced. at 7.5 f the phase margin is only 6 and at 5 f this system is unstable. two possible ceramic based capacitor solutions have been pre - sented. other capacitor combinations are certainly possible, such as a very low esr electrolytic capacitor in parallel with several microfarads of ceramic capacitance. however, there are two critical requirements that must be satisfied: 1) the zero formed by the electrolytic capacitor and its esr should be at least 1 decade higher than the 0 db crossover of the boost loop (typically around 25 khz), and 2) the ceramic capacitors must eliminate the high frequency switching spikes/edges in the boost voltage, or the lnb output noise will be too high. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
13 table 1. recommended boost capacitor characteristics quantity of capacitors value (f) tolerance (%) rating (v) temperature coefficient of capacitance size total capacitance at C10% and 20 vdc bias (f) 4 4.7 10 50 x7r 1210 14.0 3 10 10 35 x7r 1210 18.6 figure 7. gain and phase margin of the boost loop at various capacitance values single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
14 boost filtering and lnb noise the lnb output noise depends on the amount of high-frequency noise at the boost pin. to minimize the high-frequency noise at the boost pin, the ceramic capacitors should be placed as close as possible to the boost pin. surge components the circuit shown in schematic 1 includes external diodes for surge protection. the applications information section includes d2, d3, and d4 component recommendations in table 6. this configuration and these components have successfully passed surge tests up to 1000 v/500 a, with a 1.2/50 s ? 8/20 s combination wave. recently, set-top box suppliers have increased their surge speci - fications to require surge to failure of the tvs or 4000 v, whichever occurs first. these increased surge voltages produce significantly more current in the both the external circuitry and the a8303 and A8303-1. allegro surge testing has shown that the smdj20a and lnbtvs6-221 usually fail at approximately 43 v, so all the lnbr output components (ceramic capacitors, diodes, etc.) should support at least 50 v. to protect at these higher voltage/current levels three modifica - tions must be made: ? for increased positive surge, the shunting diode from the lnb pin to the boost pin (d3, 3 a/40 v) will no longer be able to protect the body diode of the output stage. this diode must be increased to a 3 a/50 v device and be located so that it is in series with the boost pin as shown in schematics 3 and 4. in this position d3 will block surge current to the majority of the boost capacitance, but the 1 f ceramic capacitor will still filter the high frequency switching noise. ? for increased negative surge, the relatively small clamping diode (d2) from lnb to ground will no longer be sufficient. this diode must be increased from a 1 a/40 v, sod123 to a 3 a/50 v, sma device. ? for a diseqc 1.0 application, a 0.47 ?/1%/0.25 w series resistor also must be added as shown in the application drawings. the 0.47 ? resistor could be reduced if there is enough equivalent resistance in any series output components such as jumpers, inductors, or pcb traces. every application will have its own surge requirements and the surge solution can be changed. however, allegro strongly recommends incorporating a form of surge protection to prevent any pin of the a8303 and A8303-1 from exceeding its absolute maximum voltage ratings shown in this datasheet. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
15 figure 8. i 2 c? interface read and write sequences. (a) for the i 2 c? write cycle and (b) for the i 2 c? read cycle 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a1 a2 a3 a4 a5 a6 a0 0 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 ak ak control register address chip address start w sda scl ak stop stop acknowledge from lnbr (slave) acknowledge from lnbr (slave) acknowledge from lnbr (slave) 1 2 3 4 5 6 7 8 9 control data (a) write to control register d6 d5 d4 d3 d2 d1 d0 d7 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a1 a2 a3 a4 a5 a6 a0 0 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 ak ak status register address chip address start w sda scl acknowledge from lnbr (slave) acknowledge from lnbr (slave) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a1 a2 a3 a4 a5 a6 a0 1 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 ak ak status data chip address start r acknowledge from lnbr (slave) acknowledge from master (b) read from status register stop i 2 c?-compatible interface the i 2 c ? interface is used to access the internal control and status registers of the a8303 and A8303-1 . this is a serial inter - face that uses two lines, serial clock (scl) and serial data (sda), connected to a positive supply voltage via a current source or a pull-up resistor. data is exchanged between a microcontroller (master) and the a8303 and A8303-1 (slave). the master always generates the scl signal. either the master or the slave can generate the sda signal. the sda and scl lines from the a8303 and A8303-1 are open-drain signals so multiple devices may be connected to the i 2 c ? bus. when the bus is free, both the sda and the scl lines are high. sda and scl signals. sda can only be changed while scl is low. sda must be stable while scl is high. however, an exception is made when the i 2 c ? start or stop condition is encountered. see the i 2 c ? communication section for further details. acknowledge (ak) bit. the acknowledge (ak) bit indicates a good transmission and can be used two ways. first, if the slave has successfully received eight bits of either an address or control data, it will pull the sda line low (ak = 0) for the ninth scl pulse to signal good transmission to the master. second, if the master has successfully received eight bits of status data from the a8303 and A8303-1 , it will pull the sda line low for the ninth scl pulse to signal good transmission to the slave. the receiver (either the master or the slave) should set the ak bit high (ak = 1 or nak) for the ninth scl pulse if eight bits of data are not received successfully. ak bit during a write sequence. when the master sends control data (writes) to the a8303 and A8303-1 there are three instances where ak bits are toggled by the a8303 and A8303-1 . first, the a8303 and A8303-1 use the ak bit to indicate reception of a valid seven-bit chip address plus a read/write bit (r/w = 0 for write). second, the a8303 and A8303-1 use the ak bit to indicate reception of a valid eight-bit control register address. third, the a8303 and A8303-1 use the ak bit to indicate reception of eight bits of control data. this protocol is shown in figure 8(a). ak bit during a read sequence. when the master reads status data from the a8303 and A8303-1 there are four instances where ak bits are sentCthree sent by the a8303 and A8303-1 and one sent by the master. first, the a8303 and A8303-1 use the ak bit to indicate reception of a valid seven-bit chip address plus a read/write bit (r/w = 0 for write). second, the a8303 and A8303-1 use the ak bit to indicate reception of a valid eight-bit status register address. third, the a8303 and A8303-1 use the ak bit to indicate reception of a valid seven-bit chip address plus a read/write bit (r/w = 1 for read). finally, the master uses the ak bit to indicate receiving eight bits of status data from the a8303 and A8303-1 . this protocol is shown in figure 8(b). single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
16 i 2 c? communications i 2 c? start and stop conditions. the i 2 c? start condi - tion is defined by a negative edge on the sda line while scl is highconversely, the stop condition is defined by a positive edge on the sda line while scl is high. the start and stop conditions are shown in figure 8. it is possible for the start or stop condition to occur at any time during a data transfer. if either a start or stop condition is encountered during a data transfer, the a8303 and A8303-1 will respond by resetting the data transfer sequence. i 2 c? write cycle description. writing to the a8303 and A8303-1 control register requires transmission of a total of 27 bitsCthree 8-bit bytes of data plus an acknowledge bit after each byte. writing to the a8303 and A8303-1 control register is shown in figure 8(a). writing to the a8303 and A8303-1 control register requires a chip address with r/w = 0, a control register address, and the control data, as follows: ? the chip address cycle consists of a total of nine bits seven bits of chip address (a6 to a0) plus one read/write bit (r/w = 0) to indicate a write from the master followed by an acknowledge bit (ak = 0 for reception of a valid chip address) from the slave. the chip address must be transmitted msb (a6) first. the first five bits of the a8303 and A8303-1 chip address (a6 to a2) are fixed as 00010. the remaining two bits (a1 and a0) are used to select one of four possible a8303 and A8303-1 chip addresses. the dc voltage on the add pin programs the chip address. see the electrical characteristics table for the add pin voltages and the corresponding chip addresses. ? the control register address cycle consists of a total of nine bitseight bits of control register address (rc7 to rc0) from the master followed by an acknowledge bit from the slave. the control register address must be transmitted msb (rc7) first. the a8303 and A8303-1 only have one control register each, so the control register address is fixed as 00000000. ? the control data cycle consists of a total of nine bitseight bits of control data (d7 to d0) from the master followed by an acknowledge bit from the slave. the control data must be transmitted msb first (d7). the control register bits are identified in the control registers section of this datasheet. i 2 c? read cycle description. reading from the a8303 and A8303-1 status register requires transmission of a total of 36 bitsCfour 8-bit bytes of data plus an acknowledge bit after each byte. reading the a8303 and A8303-1 status register requires a chip address with r/w = 0, a status register address, an i 2 c? stop condition, an i 2 c? start condition, a repeated chip address with r/w=1, and finally the status data from the a8303 and A8303-1 . reading from the a8303 and A8303-1 status regis - ter is shown in figure 8(b). ? this 9-bit chip address cycle is identical to the chip address cycle previously described for the write control register sequence. it consists of a6 to a0, plus one read/write bit (r/w = 0) from the master, followed by an acknowledge bit from the slave and finally an i 2 c? stop condition. ? the status register address cycle consists of a total of nine bitsCeight bits of status register address (rs7 to rs0) from the master, followed by an acknowledge bit from the slave. the status register address must be transmitted msb (rs7) first. the a8303 and A8303-1 only have one status register, so the status register address is fixed at 00000000. ? the repeated chip address cycle begins with an i 2 c? start condition followed by a 9-bit cycle identical to the chip address cycle previously described for the write control register sequence. it consists of a6 to a0, plus one read/write bit (r/w = 1) from the master, followed by an acknowledge bit from the slave. ? the status data cycle consists of a total of nine bitsCeight bits of status data (rd7 to rd0) from the slave, followed by an acknowledge bit from the master. the status data is transmitted msb (rd7) first. the status register bits are identified in the status register section of this data sheet. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
17 interrupt (irq) and fault clearing the a8303 and A8303-1 provide an interrupt request pin (irq), which is an open-drain, active low output. this output may be connected to a common irq line with a suitable external pull-up resistor and can be used with other i 2 c? compatible devices to request attention from the master controller. the irq output becomes active (logic low) when the a8303 and A8303-1 recognize a fault condition. the fault conditions that will force irq active include undervoltage lockout (uvlo), overcurrent protection (ocp), and thermal shutdown (tsd). the uvlo, ocp, and tsd faults are latched in the status register and will not be unlatched until the a8303 and A8303-1 status register is successfully transmitted to the master controller (an ak bit must be received from the master). see the description in the status register section and figure 9 for further details. the a8303 and A8303-1 irq response to v in(uvlo) is controlled by the i 2 c address setting. the a8303 and A8303-1 have two methods to control the irq for uvlo fault: ? the first method uses the i 2 c address setting (address 2, address 3, or address 4). in this method while v in is below 8.70 v (typ), the a8303 and A8303-1 are disabled and the i 2 c port is inactive. after v in rises above 8.70 v (typ), the i 2 c port becomes active and the irq pin is pulled low. an i 2 c read cycle is required to report and clear the uvlo fault and set the irq pin to a logic high before the a8303 and A8303-1 can be enabled. if a brown-out occurs, such that v in drops below 8.35 v (typ), the a8303 and A8303-1 will be disabled and the i 2 c port will become inactive (note that the irq pin will remain high during this time because the a8303 and A8303-1 are disabled). after v in rises above 8.70 v (typ) the i 2 c port reactivates and the irq pin is pulled low to report that a brown-out had occurred. an i 2 c read cycle is required to report and clear the uvlo fault before the a8303 and A8303-1 can be re-enabled. a detailed timing diagram is shown in figure 10(a). ? the second method uses i 2 c address setting (address 1). in this method the i 2 c port is active when v in is above the i 2 c uvlo (6 v when v in is rising). irq transitions low when v in goes above i 2 c uvlo (6 v, v in rising), and the i 2 c read cycle resets irq to logic high even if v in is below uvlo. even though irq is cleared below uvlo, one more read cycle is required after v in goes above uvlo, to re-enable the a8303 and A8303-1. while v in is falling, irq transitions low when v in goes below uvlo, and the i 2 c read cycle resets irq to logic high. a detailed timing diagram is shown in figure 10(b). when the master device receives an interrupt, it should address all slaves connected to the interrupt line in sequence and read the status register of each to determine which device is requesting attention. as shown in figure 9, the a8303 and A8303-1 latch all conditions in the status register and set the irq to logic low when a uvlo, ocp, or tsd event occurs. the irq bit is reset to logic high and the status register is unlatched when the master acknowledges the status data from the a8303 and A8303-1 (an ak bit must be received from the master). the disable (dis) and power not good (png) conditions do not cause an interrupt and are not latched in the status register. figure 9. fault, irq, and status register timing. when a uvlo, ocp, or tsd event occurs, the irq bit is set low and the status register is latched. the irq bit is reset to high when the a8303 and A8303-1 acknowledges it is being read. the status register is unlatched when the master acknowledges the status data from the a8303 and A8303-1 . single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com stop 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a1 a2 a3 a4 a5 a6 a0 0 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 ak ak status register address chip address start w sda irq fault event, irq set low, status register latched scl acknowledge from lnbr (slave) acknowledge from lnbr (slave) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a1 a2 a3 a4 a5 a6 a0 1 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 ak ak status data chip address start r acknowledge from lnbr (slave) acknowledge from master stop irq reset status register unlatched
18 10(b). irq and fault clearing in response to undervoltage at vin (uvlo), with i 2 c address set to (address 1). in this method, the i 2 c port is active when v in is above i 2 c uvlo (6 v when v in is rising). irq transitions low when v in goes above i 2 c uvlo (6 v, v in rising), and the i 2 c read cycle resets irq to logic high even if v in is below uvlo. even though irq is cleared below uvlo, one more read cycle is required after v in goes above uvlo, to re-enable the a8303 and A8303-1 . while v in is falling, irq transitions low when v in goes below uvlo, and the i 2 c read cycle resets irq to logic high. v in t i 2 c uvlo (typ), rising: 6 v, falling: 4.2 v lnb output i 2 c read cycle i 2 c inactive enable bit (via i 2 c) i 2 c inactive uv l o thresholds irq (active low) v in 8.70 v 8.35 v brown out t lnb output i 2 c read cycle irq (active low) enable bit (via i 2 c) i 2 c inactive i 2 c inactive uv l o thresholds 10(a). irq and fault clearing in response to undervoltage at vin (uvlo), with i 2 c address set to (address 2, address 3, or address 4). in this method, while v in is below 8.70 v (typ), the a8303 and A8303-1 are disabled and the i 2 c port is inactive. after v in rises above 8.70 v (typ), the i 2 c port becomes active and the irq pin is pulled low. an i 2 c read cycle is required, to report and clear the uvlo fault and set the irq pin to a logic high, before the a8303 and A8303-1 can be enabled. if a brown-out occurs, such that v in drops below 8.35 v (typ), the a8303 and A8303-1 will be disabled and the i 2 c port will become inactive (note that the irq pin will remain high during this time because the a8303 and A8303-1 are disabled). after v in rises above 8.70 v (typ) the i 2 c port reactivates and the irq pin is pulled low to report that a brown-out had occurred. an i 2 c read cycle is required to report and clear the uvlo fault before the a8303 and A8303-1 can be re-enabled. figure 10. irq and fault clearing in response to undervoltage at vin (uvlo), showing the alternate methods, set by selection of i 2 c address single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
19 l n b v out l n b i out i s e t 4 5 m s 4 5 m s l n b s h o r t e d t o g n d i 2 c r ead cycle i r q ( a c t v e l o w ) e nable (enb bit, v i a i 2 c ) figure 11. irq and fault clearing in response to overcurrent (ocp). if the lnb output is grounded for more than 45 ms, the lnb output will be shut off, an overcurrent fault (ocp) will be latched in the status register, and the irq pin will transition low. after an ocp fault, the lnb output does not respond to the enable (enb) bit until an i 2 c read cycle is executed to report and clear the ocp fault. after a successful i 2 c read, the irq pin transitions high and the a8303 and A8303-1 can be re-enabled, provided the lnb output is no longer grounded. figure 12. irq and fault clearing in response to thermal shutdown (tsd). if the lnb junction temperature rises above 165c (typ), the lnb output will be shut off, a thermal shutdown fault (tsd) will be latched in the status register, and the irq pin will transition low. after a tsd fault, the lnb output does not respond to the enable (enb) bit until an i 2 c read cycle is executed to report and clear the tsd fault. after a successful i 2 c read, the irq pin transitions high and the a8303 and A8303-1 can be re- enabled, provided the junction temperature is below 145c (typ). t j t i 2 c read cycle irq (active low) lnb o/p tsd threshold enable bit (via i 2 c) tsd bit (via i 2 c) 165c 145c loss of cooling or stb overload single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
20 i 2 c?-compatible interface timing diagram i 2 c? -compatible timing requirements characteristics symbol min. typ. max. unit bus free time between stop/start t buf 1.3 C C s hold time start condition t hd:sta 0.6 C C s setup time for start condition t su:sta 0.6 C C s scl low time t low 1.3 C C s scl high time t high 0.6 C C s data setup time t su:dat 100 C C ns data hold time* t hd:dat 0 C 900 ns setup time for stop condition t su:sto 0.6 C C s output fall time (v fi2cout(h) to v fi2cout(l) ) t fi2cout C C 250 ns *for t hd:dat (min) , the master device must provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the scl signal falling edge. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com t su:s ta t hd: st a t su:d at t hd:d at t bu f t su:s to t hi gh t lo w sd a sc l
21 control registers (i 2 c?-compatible write register) all main functions of the a8303 and A8303-1 are controlled through the i 2 c? compatible interface via the 8-bit control register. table 2 shows the functionality and bit definitions of the control register. at power-up, the control register is initialized to all 0s. table 2. control register definition bit name function description 0 vsel0 lnb output voltage control see table 3a for a8303 output voltage selections see table 3b for A8303-1 output voltage selections the available voltages provide levels for all the common standards plus the ability to add line compensation. vsel0 is the lsb and vsel2 is the msb to the internal dac. 1 vsel1 2 vsel2 3 enb 0: disable lnb output 1: enable lnb output turns the lnb output on or off. 4 C set to 0 unused 5 C 6 C 7 C table 3b. A8303-1 output voltage selection vsel2 vsel1 vsel0 lnb (v) 1 1 1 11.667 0 0 0 13.333 0 0 1 13.667 0 1 0 14.333 0 1 1 15.667 1 0 0 18.667 1 0 1 19.000 1 1 0 19.667 table 3a. a8303 output voltage selection vsel2 vsel1 vsel0 lnb (v) 0 0 0 13.333 0 0 1 13.667 0 1 0 14.333 0 1 1 15.667 1 0 0 18.667 1 0 1 19.000 1 1 0 19.667 1 1 1 20.000 single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
22 status registers (i 2 c?-compatible read register) the main fault conditions: overcurrent (ocp), and thermal shutdown (tsd) are all indicated by setting the relevant bits in the status register. for these two fault cases, after the bit is set, it remains latched until the i 2 c? master has successfully read the a8303 and A8303-1, assuming the fault has been resolved. the undervoltage lockout (uvlo) bit indicates either v in is below v uvlo , or v reg is out of regulation. uvlo disables the lnb output and forces irq low. uvlo is a latched fault, and can only be cleared by performing an i 2 c? read cycle. the disable bit (dis) indicates the status of the lnb output. the dis is set when either a fault occurs (uvlo, ocp, tsd, or cpok) or when the lnb output is turned off using the enable bit (enb) via the i 2 c? interface. the dis bit is latched and is only reset when there are no faults and the a8303 and A8303-1 output is turned back on using the enable (enb) bit via the i 2 c? interface. the power not good (png), charge pump ok (cpok), and tone detect (tdet) bits are set based on the conditions sensed at the lnb output, vcp, and tone detect input (tdi) pins, respec - tively. these bits are not latched and, unlike the other fault bits, may become reset without an i 2 c? read sequence. the png, cpok, and tdet bits are continuously updated. there are three methods to detect when the status register changes: responding to the interrupt request (irq) pin going low, continuously polling the status register via the i 2 c? interface, or detecting a fault condition external to the a8303 and A8303-1 and performing a diagnostic poll of the a8303 and A8303-1. in any case, the master should read and re-read the status register until the status changes. table 4. status register description and irq operation bit name function latched? reset condition effect on irq pin 0 dis lnb output disabled yes lnb enabled and no faults none 1 cpok charge pump ok no v cp > v boost + 5v none 2 ocp overcurrent yes i 2 c? read and i load < i set irq set low 3 trims trim bits locked yes none none 4 png power not good no lnb voltage within range none 5 tdet tone detect no tone removed from lnb pin none 6 tsd thermal shutdown yes i 2 c? read and t j < 145c irq set low 7 uvlo vin or vreg undervoltage yes i 2 c? read and v in > 9.0 v irq set low table 5. status register bit descriptions bit name description 0 dis the dis bit is set to 1 when the a8303 and A8303-1 are disabled, (enb = 0) or there is a fault: uvlo, ocp, cpok, or tsd. 1 cpok if this bit is set low, the internal charge pump is not operating correctly (vcp). if the charge pump voltage is too low, the lnb output is disabled and the dis bit is set. 2 ocp this bit will be set to a 1 if the lnb output current exceeds the overcurrent threshold (i out(max) ) for more than the overcurrent disable time (t dis ). if the ocp bit is set to 1, then the dis bit is also set to 1. 3 trims factory use only. 4 png set to 1 when the a8303 and A8303-1 are enabled and the lnb output voltage is either too low or too high (nominally 9% from the lnb dac setting). set to 0 when the a8303 and A8303-1 are enabled and the lnb voltage is within the acceptable range (nominally 5% from the lnb dac setting). 5 tdet the tdet bit is set to 1 if a tone is detected at the tdi pin that is within the specified voltage and frequency ranges. if tonectrl = 1, the tone is being transmitted by the a8303 and A8303-1 and the tone detect low threshold is determined by v td(xmt)l . if tonectrl i = 0, it is assumed the tone is being received from an external source and the tone detect low threshold is determined by v td(rcv)l . 6 tsd the tsd bit is set to 1 if the a8303 and A8303-1 have detected an overtemperature condition. if the tsd bit is set to 1, then the dis bit is also set to 1. 7 uvlo the uvlo bit is set to 1 if either the voltage at the vin pin or the voltage at the vreg pin is too low. if the uvlo bit is set to 1, then the dis bit is also set to 1. single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
23 application information schematic 1. diseqc 2.0 applications, 12 v in 10%, 700 ma i out , surge of 1000 v, 2 , 1.2/50 s C 8/20 s combination wave l1 15uh c4 100nf d3 1a/40v c3 220nf gnd c12 100nf gnd r2 2k 3.3v d1 3a/40v c1 100nf gnd rset 37.4k gnd sda scl irq tonectrl vin r1 2k 3.3v tdo sda 8 add 9 scl 7 gnd 14 tonectrl 10 vin 15 irq 6 tdi 4 nc 18 lnb 2 b o ost 2 0 vcp 1 tcap 11 nc 19 gndlx 17 vreg 13 l x 1 6 tdo 5 pad 0 iset 12 nc 3 u1 tone xmit gnd c9 10nf c8 100nf c10 220nf r5 100 c11 10nf d2 1a/40v lnbout l2 220uh r7 10k r4 2.0 r6 10k r3 15 > 40v 100ma q2 r8 10k r9 10k gnd gnd 3000w d4 32v/500a < 0.5ohm q1 > 40v or 3x10uf c5 to c7 4x4.7uf or 1x10uf c2 2x4.7uf a8303 A8303-1 see next page for bill of materials single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
24 table 6. component selection table component characteristics recommended devices c1, c4, c8, c12 100 nf, 50 v, x5r or x7r, 0603 c2 2x: 4.7 f or 1x 10 f, 25 v, x5r or x7r, 1206 c3 220 nf, 10 v (min.) , x5r or x7r, 0603 c5, c6, c7 4x: 4.7 f, 10%, 50 v, x7r, 1210 or 3x: 10 f, 10%, 35 v, x7r, 1210 4.7 f: murata: grm32er71h475ka88 taiyo yuden: umk325b7475km avx: 12105c475kat2a 10 f: murata: grm32er7ya106k c9, c11 10 nf, 50 v, x5r or x7r, 0603 c10 220 nf, 50 v, x5r or x7r, 0603 d1 schottky diode, 3 a, 40 v, sma sanken: sfpb-74 vishay: b340a-e3/5at diodes, inc.: b340a-13-f central semiconductor: cmsh3-40ma d2, d3 schottky diode, 1 a, 40 v, sod-123 diodes, inc.: b140hw-7 central semiconductor: cmmsh1-40 d4 tvs, 20 vrm, 32 vcl at 500 a, 3000 w littelfuse: smdj20a st: lnbtvs6-221s l1 15 h, 20%, i sat 3.1 a, dcr < 75 m? cooper bussmann: dr1040-150-r tdk: vlf10045t-150m3r5 sumida: cdrh10d43fbnp-150m l2 220 h, 20%, i sat 800 ma, dcr < 0.8 ? cooper bussmann: dr1040-221-r tdk: vlf10045t-221mr90 q1 mosfet, p-channel, 50 v, < 0.5 ?, sot-23 vishay: si2309ds-t1-e3 diodes, inc.: zxmp6a13fta q2 transistor, npn, 50 v, 100 ma, sot-323 diodes, inc.: bc846aw-7-f nxp: bc846w on semiconductor: bc846awt1g r1, r2 resistor, 2 k?, 1%, 0402 or 0603 r3 resistor, 15 ?, 1%, 0402 or 0603 r4 resistor, 2.0 ?, 1%, 0402 or 0603 r5 resistor, 100 ?, 1%, 0402 or 0603 r6, r7, r8, r9 resistor, 10 k?, 1%, 0402 or 0603 rset resistor, 37.4 k?, 1%, 0402 or 0603 single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
25 l1 15uh c4 100nf d3 3a/40v c3 220nf gnd c12 100nf gnd r2 2k 3.3v d1 3a/40v c1 100nf gnd rset 37.4k gnd sda scl irq tonectrl vin r1 2k 3.3v tdo sda 8 add 9 scl 7 gnd 14 tonectrl 10 vin 15 irq 6 tdi 4 nc 18 lnb 2 b o ost 2 0 vcp 1 tcap 11 nc 19 gndlx 17 vreg 13 l x 1 6 tdo 5 pad 0 iset 12 nc 3 u1 gnd c9 10nf c8 100nf c10 220nf r5 100 c11 10nf d2 1a/40v lnbout 3000w d4 32v/500a or 3x10uf c5 to c7 4x4.7uf or 1x10uf c2 2x4.7uf a8303 A8303-1 schematic 2. diseqc 1.0 applications, 12 v in 10%, 700 ma i out , surge of 1000 v, 2 , 1.2/50 s C 8/20 s combination wave single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
26 l1 15uh c4 100nf d3 3a/50v c3 220nf gnd c9 10nf c12 100nf gnd c8 100nf r2 2k 3.3v d1 3a/50v c10 220nf c1 100nf gnd gnd r5 100 c11 10nf rset 37.4k gnd sda scl irq tonectrl vin d2 3a/50v r1 2k 3.3v tdo lnbout sda 8 add 9 scl 7 gnd 14 tonectrl 10 vin 15 irq 6 tdi 4 nc 18 lnb 2 b o ost 2 0 vcp 1 tcap 11 nc 19 gndlx 17 vreg 13 l x 1 6 tdo 5 pad 0 iset 12 nc 3 u1 l2 220uh r7 10k < 0.5ohm q1 50v r4 2.0 r6 10k r3 15 50v 100ma q2 r8 10k r9 10k gnd gnd tone xmit c13 1uf 3000w d4 32v/500a or 3x10uf c5 to c7 4x4.7uf or 1x10uf c2 2x4.7uf a8303 A8303-1 schematic 3. diseqc 2.0 applications for increased surge requirements 1000 v, 2 ?, 1.2/50 s C 8/20 s combination wave, and stress to tvs failure (or 4000 v) test single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
27 schematic 4. diseqc 1.0 applications for increased surge requirements 1000 v, 2 ?, 1.2/50 s C 8/20 s combination wave, and stress to tvs failure (or 4000 v) test l1 10uh c4 100nf d3 3a/50v c3 220nf gnd gnd c12 100nf r2 2k 3.3v d1 3a/50v c1 100nf gnd rset 37.4k gnd sda scl irq tonecntl vi n r1 2k 3.3v tdo c13 1uf gnd c9 10nf c8 100nf c10 220nf r5 100 c11 10nf d2 3a/50v lnbout 3000w d4 32v/500a r10 0.47, 1/4w sda 8 add 9 scl 7 gnd 14 tonectrl 10 vi n 15 irq 6 tdi nc 3 lnb 2 b o ost 20 vcp 1 tcap 11 nc 19 gnd lx 17 vreg 13 l x 16 tdo 5 pad 0 iset 12 nc 18 4 u1 or 2x10uf c5 to c7 3x4.7uf 1x10uf c2 a8303 A8303-1 or 2x4.7uf single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
28 package es 20-pin mlp/qfn package outline drawing single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com 0.95 c seating plane c 0.08 21x 20 20 2 1 1 2 20 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wggd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-21bm) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.30 0.50 4.10 0.50 0.75 0.05 0.40 0.10 2.45 2.45 0.25 +0.05 ?0.07 4.00 0.10 4.00 0.10 2.45 2.45 b pcb layout reference view
29 i 2 c? is a trademark of philips semiconductors. diseqc? is a trademark of eutelsat s.a. copyright ?2011-2019, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. copies of this document are considered uncontrolled documents. revision history number date description 5 january 11, 2016 corrected terminal list table (page 3) 6 july 22, 2016 updated component selection table (page 22) 7 january 11, 2018 minor editorial updates 8 january 22, 2019 minor editorial updates 9 february 8, 2019 product status changed to pre-end-of-life for the latest version of this document, visit our website: www.allegromicro.com single lnb supply and control voltage regulator a8303 and A8303-1 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com

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